1. Field of the Invention
The present invention relates to minimizing the effects of temperature and of manufacturing processing on the delay of a buffer while providing a fast buffer circuit propagation delay.
2. Background Information
Many electronic systems are built using backplane interconnections arrangement for sharing information and data among the various functions in particular systems. Since the systems and the backplane interconnections are arbitrarily dispersed and/or bussed to a number of different systems, the interconnection line impedance loading is uncontrolled. In such systems high speed edges may cause system errors. The uncontrolled termination impedance mismatches and line lengths of the interconnecting transmission lines result in extended ringing with high voltage swings that may interfere with logic functions. Moreover, the high speed edges will capacitively couple to other signal lines causing errors, and magnetic coupling among signal lines when currents abruptly change due to impedance anomalies also may cause logic errors. The troublesome fast edges necessitate use of slow edges that remain slow over operating conditions.
Backplanes are routinely used to interconnect high speed microprocessors system, mass memories, cache, communications systems, displays, keyboards, printers and other typical peripherals found in such systems. High speed edges cause problems in such systems.
Buffers driving backplanes are designed with slow slew rates to reduce the problems discussed just above. In addition, temperature compensated buffers are being designed, but such designs ignore the buffer circuit delay and the effects of power supply variations and process variations.
U.S. Pat. No. 6,437,622 illustrates the state of the known by providing for slow edges that are temperature compensated so that the slow edges change little with changes in temperature. The slow edges are achieved by xe2x80x9ccurrent starvingxe2x80x9d the gates of the output MOS transistors P1 and N1. By slowly driving the gates, the output edges are correspondingly slow. The inventive FIG. 1 taken from the U.S. Pat. No. 6,437,622 illustrates the to design. Here the current sources that slowly drive or starve the gates of transistors P1 and N1. In this design, the gate current adjusts with temperature to compensate for the slew rate changes of the drive transistors P1 and N1. More gate current is supplied at higher temperatures.
FIG. 2 illustrates the output of the buffer circuit as in FIG. 1. A difference in propagation delay of one nanosecond or more over process voltage and temperature is common with such designs. FIG. 2 shows the output waveform for 4 extreme PVT conditions including, corner (concurrent extremes of several parameters) process conditions, low and high VCCs and extreme temperatures. Trace 20 compared to trace 22 illustrates the variation due to a temperature change from +110 C. to xe2x88x9240 C. Trace 20 compared to trace 24 shows the variation from a xe2x80x9cfastxe2x80x9d to a xe2x80x9cslowxe2x80x9d process concurrent with a Vcc change from +3.45V to +3.15V. Trace 26 is a trace at +3.15V, xe2x88x9240 C. and with a slow process. The same parameter variations are shown in FIG. 4 with the inventive circuitry where the delay of one nanosecond in FIG. 2 is reduced to less than 0.1 nanoseconds 40.
The output transistors P1 and N1 of FIG. 1, exhibit thresholds that must be reached before the transistors respond. The low current necessarily will slowly drive the gates resulting in a circuit delay before the transistors begin to respond. In practical designs higher temperatures weaken the output drive MOS transistors, and, when combined power supply variations and chip making variations, nanoseconds of delay may be incurred.
But, in known designs, the delay of the buffer is excessive and uncontrolled with respect to temperature and variations in the manufacturing processes that naturally occur over time.
It is an objective of the present invention to minimize buffer delay and variation thereof with respect to changing operating conditions and manufacturing variations.
In view of the foregoing background discussion, the present invention provides a buffer circuit and a process for driving an output signal where an output drive transistor defines a control input, preferably a gate of a MOS transistor, that is driven in response to an input logic signal, slowly in the positive and the negative directions to thereby produce slow edges at the buffer""s output. The present invention additionally provides pulses of current of both polarities that are triggered at the start of a positive and a negative logic transition. The pulse of current lasts only for enough time to overcome any thresholds that must be overcome before the buffer circuit output begins to react to the control input is signal. Preferably the pulses are provided by a one shot timing circuit triggered by the logic input signal. The timed output of the one shots activate switches to connect higher level current sources to the control input of the buffer circuit.
In a preferred embodiment, the one shot timing pulses can be designed with to compensate for temperature, process, and supply voltage variations such that the buffer circuit delay remains substantially constant over such variations. Typically, the one shot timing pulse will become longer with rising temperature, with slower transistor fabrication processes and with lower supply voltages.
Digital systems including computers or processing systems, communications, memories, and virtually any other digital system will find advantages implementing the present invention.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.